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M69AW048B
32 Mbit (2M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIMES: 70ns LOW STANDBY CURRENT: 100A DEEP POWER-DOWN CURRENT: 10A BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O 8 WORD PAGE ACCESS CAPABILITY: 18ns WIDE OPERATING TEMPERATURE - TA = -30 to +85C POWER-DOWN MODES - Deep Power-Down - 4 Mbit Partial Array Refresh - 8 Mbit Partial Array Refresh - 16 Mbit Partial Array Refresh
Figure 1. Package
FBGA
TFBGA48 (ZB) 6x8 mm
November 2004
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M69AW048B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description of Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Power-Down Configuration Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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M69AW048B
Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 11. Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. UB/LB Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Page Address and Chip Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . 16 Figure 11.Random and Page Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . 17 Table 12. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14.Write Enable and UB/LB Controlled, Write AC Waveforms 1 . . . . . . . . . . . . . . . . . . . . . 20 Figure 15.Write Enable and UB/LB Controlled, Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . 20 Figure 16.Write Enable and LB/UB Controlled, Write AC Waveforms 3 . . . . . . . . . . . . . . . . . . . . . 21 Figure 17.Write Enable and LB/UB Controlled, Write AC Waveforms 4 . . . . . . . . . . . . . . . . . . . . . 21 Figure 18.Chip Enable Controlled, Read Followed by Write Mode AC Waveforms . . . . . . . . . . . . 22 Figure 19.E1, W, G Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . 22 Figure 20.Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms . . . 23 Figure 21.Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC Waveforms 23 Table 13. Standby/Power-Down Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 22.Power Down Program AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 23.Power-Down Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 24.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 25.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 26.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 26 Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M69AW048B
SUMMARY DESCRIPTION
The M69AW048B is a 32 Mbit (33,554,432 bit) CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW048B is a member of STMicroelectronics PSRAM memory family. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface. The internal control logic of the M69AW048B handles the periodic refresh cycle, automatically, and without user involvement. Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB). The device can be put into standby mode using Chip Enable (E1) or in Power-Down mode by using Chip Enable (E2). The device features various kinds of Power-Down modes for power saving as a user configurable option: The Partial Array Refresh (PAR) performs a limited refresh of the part of the PSRAM array (4 Mbits, 8 Mbits, 16Mbits) that contains essential data. Deep Power-Down mode: this mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the powerdown should be less than the maximum period for refresh.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20 Address Input Data Input/Output Chip Enable, Power Down Output Enable Write Enable Upper Byte Enable Lower Byte Enable Supply Voltage Ground Not Connected (no internal connection)
VCC
DQ0-DQ15 E1, E2
21 A0-A20 W E1 E2 G UB LB M69AW048B
16 DQ0-DQ15
G W UB LB VCC VSS NC
VSS
AI05844c
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M69AW048B
Figure 3. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
LB
G
A0
A1
A2
E2
B
DQ8
UB
A3
A4
E1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
W
DQ7
H
A18
A8
A9
A10
A11
A20
AI07242
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M69AW048B
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. Data Inputs/Outputs (DQ0-DQ7). The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E1). When asserted (Low), the Chip Enable, E1, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2). The Chip Enable, E2, puts the device in Power-down mode (Deep Power-Down, PAR and Standby) when it is driven Low. One of these, Deep Power-Down mode, is the lowest power mode. Output Enable (G). The Output Enable, G, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Write, etc.) and for driving the refresh logic, even when the device is not being accessed. VSS Ground. The VSS Ground is the reference for all voltage measurements.
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Figure 4. Block Diagram
INTERNAL CLOCK GENERATOR ROW DECODER
ARBITRATION LOGIC REFRESH CONTROLLER
ADDRESS
DYNAMIC MEMORY ARRAY
E1 E2 G W LB UB VCC VSS POWER CONTROLLER CONTROL LOGIC
INPUT/OUTPUT BUFFER COLUMN DECODER
DQ0-DQ7 DQ8-DQ15
ADDRESS
AI07221b
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M69AW048B
OPERATION
Operational modes are determined by device control inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2., Operating Modes). Power-Up Sequence Because the internal control logic of the M69AW048B needs to be initialized, the following Power-Up procedure must be followed before the memory is used: - Apply power and wait for VCC to stabilize, - Wait 300s while driving both Chip Enable signals (E1 and E2) High. See Figures 12, 13, 14, 15, 16 and 17 and Table 12., Write Mode AC Characteristics, for details of when the outputs become valid. Standby Mode The device is in Standby mode when: - Chip Enable (E1) is High and - Chip Enable (E2) is High The input/output buffers and the decoding/control logic are switched off, but the dynamic array continues to be refreshed. In this mode, the memory current consumption, ISB, is reduced, and the data remains valid. See Figures 17 and Table 13., Standby/PowerDown Mode AC Characteristics, for details of when the outputs become valid. Power-down Modes Description of Power-Down Modes. The M69AW048B has four Power-down modes, Deep Power-Down, 4 Mbit Partial Array Refresh, 8 Mbit Partial Array Refresh, and 16 Mbit Partial Array Refresh (see Table 4. and Figure 22.). These can be entered using a series of read and write operations. Each mode has following features. The default state is Deep Power-Down and it is the lowest power consumption but all data will be lost once E2 is brought Low for Power-down. No sequence is required to put the device in Deep Power-Down mode after Power-up. The device is in one of the Power-down modes when: - Chip Enable (E2) is Low All the device logic is switched off and all internal operations are suspended. This gives the lowest power consumption. In this operating mode, no refresh is performed, and data is lost if the duration is longer than 10ns. This mode is useful for those applications where the data contents are no longer needed, and can be lost, but where reduced current consumption is of major importance. Power-Down Program Sequence. The PowerDown Program sequence is used to program the Power-Down Configuration. It requires a total of six read and write operations, with specific addresses and data. Between each read or write operation the device must be in Standby mode. Table 4. shows the sequence. In the first cycle, the Byte at the highest memory address (MSB) is read. In the second and third cycles, the data (RDa) read by first cycle are written back. If the third cycle is written into a different address, the sequence is aborted, and the data written by the third cycle is valid as in a normal write operation. In the fourth and fifth cycles, the Power-Down Configuration data is written. The data of the fourth cycle must be
See also Figure 24. for details on the Power-Up AC waveforms. Read Mode The device is in Read mode when: - Write Enable (W) is High and - Output Enable (G) Low and - the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The time taken to enter Read mode (tELQV, tGLQV or tBLQV) depends on which of the above signals was the last to reach the appropriate level. Data out (DQ15-DQ0) may be indeterminate during tELQX, tGLQX and tBLQX but data will always be valid during tAVQV. See Figures 7, 8, 9, 10 and 11 and Table 11., Read Mode AC Characteristics, for details of when the outputs become valid. Write Mode The device is in Write mode when - Write Enable (W) is Low and - Chip Enable (E1) is Low and E2 is High - at least one of Upper Byte Enable (UB) and Lower Byte Enable (LB) is Low. The Write cycle begins just after the event (the falling edge) that causes the last of these conditions to become true (tAVWL or tAVEL or tAVBL). The Write cycle is terminated by the rising edge of Write Enable (W) or Chip Enable (E1), whichever occurs first. If the device is in Write mode (Chip Enable (E1) is Low, Output Enable (G) is Low, Upper Byte Enable (UB) and/or Lower Byte Enable (LB) is Low, then Write Enable (W) will return the outputs to high impedance within tWHDZ of its rising edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable (W), or for tDVEH before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tBHDZ, tWHDZ, tEHDZ.
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set to `0000h', and the data of the fifth cycle is the Power-Down Configuration data (see Table 5., Power-Down Configuration Data). If the fourth cycle is written into a different address, the sequence is aborted. In the last cycle, a read is made from the specific Power-Down Configuration address (see Table 6., Power-Down Configuration Addresses). The Power-Down Configuration data Table 2. Operating Modes
Operation Standby (Deselected) Power-Down (2) No Read (1) Lower Byte Read (1) Lower Byte Write (1) No Write Upper Byte Read (1) Upper Byte Write (1) Word Read (1) Word Write (1) E1 VIH X VIL VIL VIL VIL VIL VIL VIL VIL E2 VIH VIL VIH VIH VIH VIH VIH VIH VIH VIH W X X VIH VIH VIL VIL VIH VIL VIH VIL G X X VIL VIL VIH VIH VIL VIH VIL VIH(3) LB X X VIH VIL VIL VIH VIH VIH VIL VIL UB X X VIH VIH VIH VIH VIL VIL VIL VIL DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Output Data Input Hi-Z Hi-Z Hi-Z Data Output Data Input DQ8-DQ15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input Data Output Data Input Power Standby (ISB) Power-Down (ICCPD, ICCP4, ICCP8, ICCP16) Output Disable Active (ICC) Active (ICC) Output Disable Active (ICC) Active (ICC) Active (ICC) Active (ICC)
and address must correspond, otherwise the sequence is aborted. When this sequence is performed to take the device from one PAR mode to another, the write data may be lost. So, if a PAR mode is used, this sequence should be performed prior to any normal read or write operations.
Note: X = VIH or VIL. 1. Should not be kept in this logic condition for a period longer than 1s. 2. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data retention depend on the selection of Power-Down programming. 3. G can be VIL during the Write operation if the following conditions are satisfied: a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied; b. G stays VIL during the entire Write cycle.
Table 3. Power-Down Modes
Mode Deep Power-Down (Default) 4Mb PAR 8Mb PAR 16Mb PAR Data Retention No 4 Mbit 8 Mbit 16 Mbit Retention Address N/A 00000h - 3FFFFh 00000h - 7FFFFh 00000h - FFFFFh
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Table 4. Power-Down Program Sequence
Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh PDC Address(1) Data Read Data (RDa) RDa RDa 0000h PDC Data(1) Read Data (RDb)
Note: 1. PDC Power-Down Configuration.
Table 5. Power-Down Configuration Data
Power-Down Configuration Data Power-Down Modes DQ15-DQ9 Deep Power-Down (default) 4Mb PAR 8Mb PAR 16Mb PAR 0 0 0 0 DQ8-DQ2 0 0 0 0 DQ1 1 1 0 0 DQ0 1 0 1 0
Table 6. Power-Down Configuration Addresses
Power-Down Configuration Addresses Power-Down Modes A20 Deep Power-Down (default) 4Mb PAR 8Mb PAR 16Mb PAR 1 0 1 0 A19 1 1 0 0 A18-A0 1 1 1 1 Binary 1FFFFFh 0FFFFFh 17FFFFh 07FFFFh
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M69AW048B
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 7. Absolute Maximum Ratings
Symbol IO TA TSTG VCC VIO Output Current Ambient Operating Temperature Storage Temperature Core Supply Voltage Input or Output Voltage Parameter Min -50 -30 -55 -0.5 -0.5 Max 50 85 125 3.6 3.6 Unit mA C C V V
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
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M69AW048B
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 8., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 8. Operating and AC Measurement Conditions
M69AW048B Parameter Min VCC Supply Voltage1 Ambient Operating Temperature Load Capacitance (CL) Output Circuit Protection Resistance (R1) Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages Input Transition Time2 (t) between VIL and VIH 0 VCC/2 VRL = 0.3VCC; VRH = 0.7VCC 5 2.7 -30 50 50 VCC 70 Max 3.3 85 V C pF V V V ns Unit
Note: 1. All voltages are referenced to VSS. 2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8.
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VCC/2
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL Output Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI04831
OUT
0V
CL includes JIG capacitance
AI07222c
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M69AW048B
Table 9. Capacitance
Symbol CIN COUT Parameter Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 5 8 Unit pF pF
Table 10. DC Characteristics
Symbol ICC1 VCC Active Current ICC2 Parameter Test Condition VCC = 3.3V, VIN = VIH or VIL, E1 = VIL and E2 = VIH, IOUT = 0mA tRC / tWC = minimum tRC / tWC = 1 s Min Max 30 3 Unit mA mA
ICC3
VCC Page Read Current
VCC = 3.3V, VIN = VIH or VIL, E1 = VIL and E2 = VIH, IOUT = 0mA, tPRC = min. Deep PowerDown 4 Mb PAR 8 Mb PAR 16 Mb PAR
10
mA
ICCPD ICCP4 ICCP8 ICCP16 ILI ILO ISB VIH (1) VIL (2) VOH VOL Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VCC Power Down Current VCC = 3.3V, VIN = VIH or VIL, E2 0.2V
10 40 50 65 -1 -1 1 1 100 0.8VCC -0.3 VCC + 0.2 0.2VCC
A A A A A A A V V V
0V VIN VCC 0V VOUT VCC VCC = 3.3V, VIN 0.2V or VIN VCC -0.2V, E1 = E2 VCC -0.2V
VCC = 2.7V, IOH = -0.5mA IOL = 1mA
2.4 0.4
V
Note: 1. Maximum DC voltage on input and I/O pins is VCC + 0.2V. During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns. 2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns.
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M69AW048B
Table 11. Read Mode AC Characteristics
Symbol tAVAX (1,2) tAVAX2 (1,6,7) tAVEH2 (1,6,7) tAVEL tAVGL tAVQV (3,5) tAVQV2 (3,6) tAXAV (5,8) tAXAV2 (6,8) tAXQX (3) tBHQX (3) tBHQZ (4) tBLQV (3) tBLQX (4) tEHAX (9) tEHEL tEHQX
(3)
Alt. tRC tPRC tPRC tASC tASO tAA tPAA tAX tAXP tOH tOH tBHZ tBA tBLZ tCHAH tCP tOH tCHZ tRC tRC tCE tCLZ tOHAH tOH tOHZ tOE tOLZ Address Valid Time
Parameter
M69AW048B Min 70 25 25 -5 10 70 18 10 10 3 3 20 30 0 -5 15 3 20 70 70 1000 1000 70 3 -5 3 20 40 0 Max 1000 1000 1000
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Page Read Cycle Time Page Read Cycle Time Address Valid to Chip Enable Low Address Valid to Output Enable Low Address Valid to Output Valid Page Address Access Time Address Invalid Time Page Address Invalid Time Data hold from address change Upper/Lower Byte Enable High to Output Transition Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable Low to Output Transition Chip Enable High to Address Invalid Chip Enable High to Chip Enable Low Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Read Cycle Time Read Cycle Time Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Address Invalid Output Data Hold Time Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition
tEHQZ (4) tELAX (1,2) tELEH (1,2) tELQV (3) tELQX (4) tGHAX tGHQX
(3)
tGHQZ (4) tGLQV (3) tGLQX (4)
Note: 1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Address should not be changed within minimum Read Cycle Time. 3. The output load 50pF with 50 termination to VCC*0.5 V. 4. The output load 5pF without any other load. 5. Applicable to A3 to A20 when E1 is kept Low. 6. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access. 7. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4s. In other words, Page Read Cycle must be closed within 4s. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.
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M69AW048B
Figure 7. Read Mode AC Waveforms
tELEH A0-A20 tAVEL tELQV E1 tEHEL tGLQV G tBLQV LB, UB tBLQX tGLQX tELQX DQ0-DQ15 VALID DATA OUTPUT
AI08986
ADDRESS VALID
VALID tAVEL tEHAX
tEHQZ
tGHQZ
tBHQZ tEHQX
Note: E2 = High, W = High.
Figure 8. Output Enable Controlled, Read Mode AC Waveforms
tAXAV A0-A20
tAVAX ADDRESS VALID tAVQV tAXAV
tAVAX ADDRESS VALID tAVQV tAXAV
E1 tAVGL G tGHQX UB, LB tGLQX DQ0-DQ15 tAXQX DATA OUT DATA OUT
AI08987
tGLQV
tGHAX
tGHQZ
Note: Write Enable (W) = High, E2 = High.
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M69AW048B
Figure 9. UB/LB Controlled, Read Mode AC Waveforms
tAXAV A0-A20 tAVQV E1 LB tBHQZ tBLQV tBHQZ Low tBLQV tBLQV tAVAX ADDRESS VALID tAXAV
UB
tBLQX DQ0-DQ7
tBHQX VALID DATA OUT
tBLQX
tBHQX VALID DATA OUT tBHQZ
tBLQX DQ8-DQ15
tBHQX VALID DATA OUTPUT
ai08990
Note: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Page Address and Chip Enable Controlled, Read Mode AC Waveforms
tELEH A20-A3 tAVAX A2-A0 tAVEL tAVQV E tELQV G tEHQZ ADDRESS VALID tELAX tAXAV2 ADDRESS VALID tAVAX2 ADDRESS VALID tAVQV2 tAVAX2 ADDRESS VALID tAVQV2 tAXAV2 tAVEH ADDRESS VALID tAVQV2 tAXAV2 tEHAX
LB, UB tELQX DQ0-DQ15 tAXQX VALID DATA OUTPUT tAXQX VALID DATA OUTPUT tAXQX VALID DATA OUTPUT VALID DATA OUTPUT tEHQX
AI08991
Note: Write Enable (W) = High, E2 = High.
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M69AW048B
Figure 11. Random and Page Address Controlled, Read Mode AC Waveforms
tAXAV A20-A3 tAVAX ADDRESS VALID tAXAV2 tAVAX A2-A0 tAVQV E Low tGLQV G tBLQV LB, UB tGLQX tBLQX DQ0-DQ15 tAXQX DATA OUT (Normal Access) tAXQX tAXQX DATA OUT (Normal Access) tAXQX ADDRESS VALID tAVQV2 tAXAV tAVAX2 ADDRESS VALID tAVAX ADDRESS VALID tAXAV2 tAVAX ADDRESS VALID tAVQV tAVAX2 ADDRESS VALID tAVQV2 tAXAV
DATA OUT (Page Access)
DATA OUT (Page Access)
AI08992
Note: E2 = High.
17/29
M69AW048B
Table 12. Write Mode AC Characteristics
M69AW048B Symbol tAVAX (1,2) tAVBL (2) tAVEL (2) tAVWL (2) tAXAV (5) tBHAX (4) tBHDZ tBLBH (3) tBLBH2 tBLWH (3) tDVBH tDVEH tDVWH tEHAX (4) tEHDZ tEHEL tELAX (1,2) tELEH (3) tGHAV (7) tGHEL (6) tGHDZ (4) tWHAX (4) tWHDZ tWLBH (3) tWLWH (3) Alt. tWC tAS tAS tAS tAXW tBR tDH tBW tBWO tBW tDS tDS tDS tWRC tDH tCP tWC tCW tOES tOHCL tOHZ tWR tDH tWP tWP Write Cycle Time Address Valid to LB, UB Low Address Valid to Chip Enable Low Address Valid to Write Enable Low Address Invalid Time for Write LB, UB High to Address Transition LB, UB High to Input High-Z LB, UB Low to LB, UB High LB, UB Low to LB, UB High for Page Access LB, UB Low to Write Enable High Input Valid to LB, UB High Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip Enable High to Input High-Z Chip Enable High to Chip Enable Low Write Cycle Time Chip Enable Low to Chip Enable High Output Enable High to Address Valid Output Enable High to Chip Enable Low Output Enable High to Output Hi-Z Write Enable High to Address Transition Write Enable High to Input High-Z Write Enable Low to LB, UB High Write Enable Low to Write Enable High 15 0 45 45 15 0 45 20 45 20 20 20 15 0 15 70 45 0 -5 20 1000 1000 Parameter Min 70 0 0 0 10 1000 Max 1000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Maximum value is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Minimum value must be equal to or greater than the sum of write pulse (tELEH, tWLBH or tBLBH) and write recovery time (tEHAX, tWHAX or tBHAX). 3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last. 4. Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first. 5. Applicable to any address change when E1 stays Low. 6. If G is Low after minimum tGHEL, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met. 7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met.
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M69AW048B
Figure 12. Chip Enable Controlled, Write AC Waveforms
tELAX A0-A20 ADDRESS VALID tEHAX tAVEL E1 tWHAX tAVWL W tBHAX tAVBL LB, UB tGHEL G tDVEH tDVWH tDVBH VALID DATA INPUT
ai08993
ADDRESS VALID
tELEH
tAVEL
tWLWH
tAVWL
tBLWH
tAVBL
tEHDZ tWHDZ tBHDZ
DQ0-DQ15
Note: E2 = High.
Figure 13. Write Enable Controlled, Write AC Waveforms
tAXAV A0-A20 tAVAX ADDRESS VALID tAVAX ADDRESS VALID
E1
Low tAVWL
tWHAX tWLWH tAVWL tWLWH tWHAX
W
LB, UB tGHAV G tDVWH tGHDZ DQ0-DQ15 VALID DATA INPUT tWHDX tDVWH VALID DATA INPUT
AI08994b
tWHDZ
Note: E2 = High.
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M69AW048B
Figure 14. Write Enable and UB/LB Controlled, Write AC Waveforms 1
tAVAX A0-A20 ADDRESS VALID tAXAV E1 Low tAVWL W LB tBHAX tBHAX tWLBH tAVWL tWLBH tAVAX ADDRESS VALID
UB
tDVBH DQ0-DQ7 VALID DATA INPUT
tBHDZ
tDVBH DQ8-DQ15 VALID DATA INPUT
tBHDZ
AI08995b
Note: E2 = High.
Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 2
tAXAV A0-A20 tAVAX ADDRESS VALID tAXAV E1 Low tAVBL W LB tWHAX tWHAX tBLWH tBLWH tAVAX ADDRESS VALID
tAVBL UB
tDVWH DQ0-DQ7 VALID DATA INPUT
tWHDZ
tDVWH DQ8-DQ15 VALID DATA INPUT
tWHDZ
AI08996b
Note: E2 = High.
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M69AW048B
Figure 16. Write Enable and LB/UB Controlled, Write AC Waveforms 3
tAVAX tAXAV A0-A20 E1 Low tAVBL W LB tBHAX tBHAX tBLBH ADDRESS VALID tAXAV tBLBH ADDRESS VALID tAVAX
tAVBL UB
tDVBH DQ0-DQ7 VALID DATA INPUT
tBHDZ
tBVWH DQ8-DQ15 VALID DATA INPUT
tBHDZ
AI08997b
Note: E2 = High.
Figure 17. Write Enable and LB/UB Controlled, Write AC Waveforms 4
tAXAV A0-A20 tAVAX ADDRESS VALID Low tAXAV tAVAX ADDRESS VALID
E1
W tBHAX LB tAVBL tBLBH tAVBL tBLBH tBHAX
tAVBL tDVBH DQ0-DQ7
tBLBH2 tBHDZ VALID DATA INPUT tBHAX tDVBH VALID DATA INPUT tBLBH2 tAVBL tBLBH tBHAX tBHDZ
UB
tBLBH
tDVBH DQ8-DQ15 VALID DATA INPUT
tBHDZ tDVBH VALID DATA INPUT
tBHDZ
AI08998b
Note: E2 = High.
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M69AW048B
Figure 18. Chip Enable Controlled, Read Followed by Write Mode AC Waveforms
tELAX A0-A20 tEHAX (read) E1 tEHEL W tELEH tEHEL tELQV WRITE ADDRESS tAVEL tEHAX tELAX(read) READ ADDRESS tAVEL (read) tEHAX(read)
UB, LB tGHEL G tEHQZ tEHQX DQ0-DQ15 READ DATA OUTPUT tDVEH WRITE DATA INPUT tEHDZ tELQX tEHQX READ DATA OUTPUT
ai08999b
Note: Write address is valid from either E1 or W of last falling edge.
Figure 19. E1, W, G Controlled, Read and Write Mode AC Waveforms
tELAX A0-A20 tEHAX (read) E1 tEHEL W tWLWH UB, LB tGHEL G tEHQZ tEHQX DQ0-DQ15 READ DATA OUTPUT tDVWH WRITE DATA INPUT tGLQX tWHDZ READ DATA OUTPUT
ai09400b
tELAX(read) READ ADDRESS tAVEL (read) tEHAX(read)
WRITE ADDRESS tAVEL tWHAX
tELEH
tEHEL
tELQV
tGHQV
tGHQX
Note: G can be Low fixed in write operation under E1 control read-write-read operation.
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M69AW048B
Figure 20. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms
tAXAV A0-A20 tAVAX WRITE ADDRESS tAXAV E1 Low tWLWH W tAVWL UB, LB tAVGL G tGHQZ tGHQX DQ0-DQ15 DATA OUT tDVWH DATA IN tGLQX tWHDZ tGHQZ tGHQX DATA OUT
ai09401b
tAVAX(read) READ ADDRESS tAVQV
tWHAX
tGLQV
Note: E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G.
Figure 21. Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC Waveforms
tAXAV A0-A20 tAVAX WRITE ADDRESS tAXAV E1 Low tAVAX(read) READ ADDRESS tAVQV
W tAVBL UB, LB tAVGL G tBHQZ tBHQX DQ0-DQ15 DATA OUT tDVBH DATA IN tBLQX tBHDZ tBHQZ tBHQX DATA OUT
ai09402b
tBLBH
tBHAX
tBLQV
Note: E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G.
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M69AW048B
Table 13. Standby/Power-Down Mode AC Characteristics
Symbol tCLEX tEXCH tEHEV (1) tCHEL (2) tEHCH tEHGL tEHWL
(3)
Alt. tCSP tC2LP tCHH tCHHP tCHS tCHOX tCHWX t
Parameter E2 Low Setup Time for Power Down Entry E2 Low Hold Time after Power Down Entry E1 High Hold Time following E2 High after PowerDown Exit (Deep Power-Down Mode only) E1 High Hold Time following E2 High after PowerDown Exit (not in Deep Power-Down Mode) E1 High Setup Time following E2 High after PowerDown Exit E1 High to G Invalid Time for Standby Entry E1 High to W Invalid Time for Standby Entry Input Transition Time
M69AW048B Min 10 70 300 1 0 10 10 1 25 Max
Unit ns ns s s s ns ns ns
t (4)
Note: 1. 2. 3. 4.
Applicable also to Power-up. Applicable when 4Mb, 8Mb and 16Mb PAR mode is programmed Some data might be written into any address location if tEHWL (min) is not satisfied. The Input Transition Time (t) at AC testing is 5ns as shown below. If actual t is longer than 5ns, it may violate AC specification of some timing parameters.
Figure 22. Power Down Program AC Waveforms
tAVAX A0-A20
MSB 2 MSB 2 MSB 2 MSB 2 MSB 2 PDCADD3
tAXAV E1
tAXAVL 4
G
W
LB, UB
DQ0-DQ15
RDa Cycle 1
RDa Cycle 2
RDa Cycle 3
00 Cycle 4
PDCD4 Cycle 5
RDb Cycle 6
AI07225c
Note: 1. E2 = High. 2. All address inputs must be High from Cycle 1 to Cycle 5. 3. PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherwise the data programmed during the Power-Down Program sequence may be incorrect. 4. PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwise the data programmed during the Power-Down Program sequence may be incorrect. 5. tEHEL after the end of Cycle 6, the Power Down Program is completed and the device returns to normal operation.
24/29
M69AW048B
Figure 23. Power-Down Mode AC Waveforms
E1 tEHCH E2 tCLEX DQ0-D15 tEXCH tCHEL Hi-Z
Power-Down Power-Down Mode Entry
Power-Down Exit
AI09403
Figure 24. Power-Up Mode AC Waveforms
E1 tEHEL E2
VDD
VDDmin
AI09404
Figure 25. Standby Mode Entry AC Waveforms, After Read
E1 tEHGL G tEHWL
W Read Active Standby Write Active Standby
AI09405
Note: E2 = High.
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M69AW048B
PACKAGE MECHANICAL
Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View
D FD FE SD D1
SE BALL "A1" E E1 ddd
e e A A1 b A2
BGA-Z26
Note: Drawing is not to scale.
Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.250 0.750 1.125 1.375 0.375 0.375 7.900 - - - - - - 6.000 3.750 0.350 5.900 - 0.260 0.900 0.450 6.100 - 0.100 8.100 - - - - - - 0.3150 0.2067 0.0295 0.0443 0.0541 0.0148 0.0148 0.3110 - - - - - - 0.2362 0.1476 0.0138 0.2323 - Min Max 1.200 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ Min Max 0.0472 inches
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M69AW048B
PART NUMBERING
Table 15. Ordering Information Scheme
Example: Device Type M69 = PSRAM Mode A = Asynchronous Operating Voltage W = 2.7 to 3.3V Array Organization 048 = 32 Mbit (2M x16) Option 1 B = 2 Chip Enable Option 2 L = Low Leakage Speed Class 70= 70 ns Package ZB = TFBGA48, 0.75mm pitch Operative Temperature 8 = -30 to 85 C M69AW048 B L 70 ZB 8
The notation used for the device number is as shown in Table 15.. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office.
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M69AW048B
REVISION HISTORY
Table 16. Document Revision History
Date 07-Oct-2002 10-Mar-2003 Version -01 2.0 First Issue Document completely revised Data Key and Address Key renamed Power-Down Configuration data and Power-Down Configuration Address respectively. Sleep mode renamed Deep Power-Down mode. ICCS removed and IPD renamed ICCPD in Table 10., DC Characteristics. Partial mode renamed Partial Array Refresh. Table 12. Write Mode AC Characteristics: tGHDZ added and Note 2 updated. tGHQZ changed to tGHDZ in Figure 13.Write Enable Controlled, Write AC Waveforms. AC Waveforms converted to ST standard. tELQZ, tGLQZ, tBLQZ changed into tELQX, tGLQX, tBLQX in Table 11., Read Mode AC Characteristics. VOH value updated in Table 10., DC Characteristics. Revision Details
9-Mar-2004
3.0
21-Sep-2004 15-Nov-2004
4.0 5.0
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M69AW048B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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